Conventional electronic circuits may be driven using a single supply voltage having a ground voltage for reference. Even when two supply voltages are used, the supply voltages may typically be identical with each other except for their polarities, for example, ±5 volts and/or ±3.3 volts. Such supply voltages may also be employed in connection with circuits incorporating semiconductor devices.
For systems with very fast operating speeds and/or low current consumption, electronic circuits may use a greater variety of supply voltages and/or direct current (DC) bias voltages as compared to conventional circuits. An electronic circuit configured to operate using a range of supply voltages may include a tolerant input circuit that is designed to generate an input voltage having desired characteristics, such as voltage level, rise/fall time, noise level, and/or other characteristics, in response to a signal voltage applied to an input pad of the circuit.
FIG. 1 is a circuit diagram of a conventional input circuit 100 configured to operate using a range of supply voltages.
Referring to FIG. 1, the input circuit 100 includes an electrostatic discharge (ESD) protection circuit 110, an input signal transmission circuit 120, a Schmitt trigger inverter 130, and an inverter 140.
A first supply voltage VDD1 may have a lower voltage level than a voltage level of a second supply voltage VDD0 and a third supply voltage VDDP. Further, a ground voltage GND may be 0V (volts).
The ESD protection circuit 110 discharges electrostatic charge present in an input signal applied through an input pad 105. The ESD protection circuit 110 may discharge static charge through the first supply voltage VDD0 and/or the ground voltage GND. Thus, the ESD protection circuit 110 provides the input signal applied to the input pad 105 to the input node N0 with reduced electrostatic charge. The ESD protection circuit 110 may include five MOS transistors and a resistor R configured as shown in FIG. 1. Since the structure and operation of the ESD protection circuit 110 are well known, a more detailed description of the ESD protection circuit 110 may be omitted.
The Schmitt trigger inverter 130 generates the second transmission signal at the second output node N2 in response to the first transmission signal at the first output node N1.
The input signal transmission circuit 120 generates and outputs a first transmission signal at the first output node N1 using the input signal applied at the input node N0 through the ESD protection circuit 110, in response to a second transmission signal at the second output node N2 generated at an output of the Schmitt trigger inverter 130.
The inverter 140 inverts the phase of the second transmission signal at the second output node N2 and outputs it as an output signal OUT. The inverter 140 may be used as a buffer for providing the second transmission signal at the second output node N2 to, for example, a circuit that operates based on the second transmission signal.
Each of the second supply voltage VDD0 and the third supply voltage VDDP may have a voltage of 3.3V and the first supply voltage VDD1 may have a voltage of 1V.
When a voltage of zero volts is applied to the input pad 105, the voltage level of the input signal at the input node N0 output from the ESD protection circuit 110 is also zero volts. Also, an NMOS transistor M1 having a gate to which the second supply voltage VDDP of 3.3V is applied is turned on. Consequently, the voltage level of the first transmission signal at the first output node N1 will be zero volts. The Schmitt trigger inverter 130, whose operation is controlled by the voltage of the input signal at the input node N0, may cause the second transmission signal at the second output node N2 to have a voltage level of 3.3V in response to the first transmission signal at the first output node N1 having a voltage level of zero volts. An NMOS transistor M5, which has a gate connected to the second output node N2 having a voltage level of 3.3V, is turned on, and an NMOS transistor M4 having a gate to which the first supply voltage VDD0 of 3.3V is applied is also turned on. Accordingly, since the voltage applied to the gate of a PMOS transistor M2 is zero volts, the PMOS transistor M2 is also turned on.
The NMOS transistor M1 and the PMOS transistor M2, which may form a transmission gate, may be driven through the procedures described above. When a voltage of zero volts is applied at the input node N0, a PMOS transistor M3, which has a first current terminal connected to the input node N0 and a gate to which the first supply voltage VDD1 with a voltage level of 1V is applied, remains off.
When the voltage level at the input node N0 is gradually increased to about 1.6V, the voltage between the gate and the source of the PMOS transistor M3 is −0.6V. If the threshold voltage of the MOS transistor M3 is −0.6V, current will start to flow once the voltage at the input node N0 starts to go over about 1.6V.
The second transmission signal at the second output node N2 output from the Schmitt trigger inverter 130 will change from 3.3V to 0V when the first transmission signal at the first output node N1 reaches 1.9V. However, the MOS transistors M3, M4, and M5 will remain on while the voltage applied to the input pad is increased from 1.6V to 1.9V.
Accordingly, in this voltage range, undesired leakage current may flow from the PMOS transistor M3 to the ground voltage connected to a terminal of the NMOS transistor M5. This leakage current is illustrated in the graphs on the left-hand side of FIG. 6. As shown therein, in a conventional input circuit configured to operate using a range of supply voltages, when a voltage V(PAD) of the input pad 105 is increased, a leakage current I(PAD) may flow from the input pad 105 just before and/or just after the transition of the voltage V(n2) of the second transmission signal at the second output node N2 from a high level to a low level. As the operating voltage of a system using the circuit is lowered, the difference between the voltage level of a signal input/output through the input pad and the operating voltage may increase, and the threshold voltage of MOS transistors employed in the circuit may be lowered. These changes may result in an increase in the amount of a leakage current in the circuit. Increased leakage currents may result in higher power consumption and/or shorter battery life.